1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same. More particularly, the present invention relates to the structure of a lateral bipolar junction transistor and a method of fabricating a lateral bipolar junction transistor for a high-performance bipolar LSI comprising a lateral bipolar junction transistor, a vertical bipolar junction transistor and a Schottky barrier diode, and a method of fabricating such a high-performance bipolar LSI.
2. Description of the Prior Art
A known very-high-speed bipolar junction transistor has a base contact electrode and an emitter contact electrode formed of a polycrystalline silicon film, and a base region and an emitter region formed by the diffusion of the impurity from the polycrystalline silicon film forming the emitter contact electrode in a self-alignment mode. FIGS. 21A, 21B, 21C and 21D show the very-high-speed bipolar junction transistor in different steps of the fabricating process. As shown in FIG. 21A, an n-type epitaxial layer 4 is formed after forming an embedded collector region 2 of a second conduction type, for example, n-type, and a p-type channel stop region 3 in one of the major surfaces of a silicon substrate 1 of a first conduction type, for example, p-type, a heavily doped n-type collector contact region 5 is formed so as to reach the embedded collector region 2, and then a field insulating film 6 is formed by local oxidation over the entire surface excluding the collector electrode region, and a region 4A in which a base region and an emitter region are to be formed afterward. Subsequently, a thin insulating film 7, such as a thin SiO.sub.2 film, is formed over the entire surface, a portion of the thin insulating film 7 corresponding to the region 4A is removed, a first polycrystalline silicon film 8, which serves as a base contact electrode, by a CVD process (chemical vapor deposition process), and then the polycrystalline silicon film 8 is doped with a p-type impurity, i.e., boron. Then, the p.sup.+ -type polycrystalline silicon film 8 is patterned by using a first resist mask 9 having the pattern of the base contact electrode.
Then, as shown in FIG. 21B, a SiO.sub.2 film 10 is formed over the entire surface including the patterned p.sup.+ -type polycrystalline silicon film 8 by a CVD process, and then a second resist mask 11 is formed. Portions of the SiO.sub.2 film 10 and the p.sup.+ -type polycrystalline silicon film 8 corresponding to an active region, in which an intrinsic base region and an emitter region are to be formed, are removed by selective etching using the resist mask 11 to form a window 13 and a base contact electrode 12 formed of the p.sup.+ -type polycrystalline silicon film 8.
Then, as shown in FIG. 21C, the region 4A is doped through the window 13 with a p-type impurity, i.e., boron, by ion implantation to form a link base region 14 for connecting an external base region and an intrinsic base region to be formed on the region 4A afterward. Then, a SiO.sub.2 film is formed by a CVD process, and then the SiO.sub.2 film formed by the CVD process is densified through a heat treatment in which the SiO.sub.2 film is heated at a temperature on the order of 900.degree. C. During the heat treatment of the SiO.sub.2 film, boron contained in the base contact electrode 12 formed of the p.sup.+ -type polycrystalline silicon film is caused to diffuse into the region 4A to form part of an external base region 16. Then, a SiO.sub.2 side wall 15 is formed over the inner surface of the base electrode 12 facing the window 13.
Then, as shown in FIG. 21D, a second polycrystalline silicon film 18 for an emitter contact electrode is deposited by a CVD process in a window 17 defined by the side wall 15. Then, the polycrystalline silicon film 18 is doped by ion implantation with a p-type impurity, such as B or BF.sub.2, and annealed to form a p-type intrinsic base region 19 in the active region, and then, the p-type base region 19 is doped by ion implantation with an n-type impurity, such as As, and annealed to form an n-type emitter region 20. In another method, the polycrystalline silicon film 18 is doped by ion implantation with p-type and n-type impurities and annealed to form the p-type intrinsic base region 19 and the n-type emitter region 20. During the annealing process for forming the base region 19 and the emitter region 20, boron contained in the base contact electrode 12 formed of p.sup.+ -type polycrystalline silicon is caused to diffuse to complete the external base region 16. The impurity concentration of the intrinsic base region 19 is higher than that of the link base region 14. Then, contact holes are formed, and then a base electrode 21, a collector electrode 22 and an emitter electrode 23 of a metal, such as aluminum, are formed to complete a very-high-speed bipolar transistor 24.
A high-performance bipolar junction transistor LSI comprising such an npn bipolar junction transistor, a lateral pnp bipolar junction transistor, a Schottky diode with a guardring and a LEC (low emitter concentration) transistor formed on a semiconductor substrate is being developed.
FIG. 16 shows the structure of a lateral pnp bipolar junction transistor 40. The lateral pnp bipolar junction transistor 40 is constructed by forming an n-type epitaxial layer 4 over an n-type embedded base region 26 formed on a p-type silicon substrate 1, forming a field insulating film 6 by selective oxidation, forming an n-type plug-in region 27 reaching the n-type embedded base region 26, and an n-type base contact region 28, forming a p-type collector region 32 and a p-type emitter region 33 respectively having heavily doped p-type regions 30 and 31, and forming an aluminum collector electrode 34, an aluminum base electrode 35 and an aluminum emitter electrode 36. In FIG. 16, indicated at 37 is a p-type isolating region, at 38 is a layer insulating film and at 39 is a thin SiO.sub.2 film. In most cases, the p-type collector region 32 and the p-type emitter region are formed at the same time with the p-type intrinsic base region 19 of the npn bipolar junction transistor 24, and the heavily doped p-type regions 30 and 31 are formed at the same time with the external base region 16 of the npn bipolar junction transistor 24. The base width W.sub.B is determined by the p-type collector region 32 and the p-type emitter region 33. FIG. 17 shows the impurity concentration profile of a section along an alternate long and short dash line 41. The impurity concentration profile has a peak at a position corresponding to a portion near the surface of the substrate as shown in FIG. 17, because the surface is doped by ion implantation with boron and boron is caused to diffuse in forming the p-type collector region 32 and the p-type emitter region 33. Accordingly, the collector region 32 and the emitter region are nearest in the vicinity of the surface.
FIG. 18 shows the structure of another lateral pnp bipolar junction transistor 42, in which portions corresponding to those of the lateral pnp bipolar junction transistor shown in FIG. 16 are denoted by the same reference characters and the description thereof will be omitted to avoid duplication. In fabricating the lateral pnp bipolar junction transistor 42, a base contact region 28 is formed simultaneously with the collector contact region 5 of a npn bipolar junction transistor 24, and a p-type emitter region 33 and a p-type collector region 32 are formed simultaneously with the external base region 16 of the npn bipolar junction transistor 24 through the diffusion of boron from a contact electrodes 44 and 43 formed of p.sup.+ -type polycrystalline silicon. Indicated at 3 is a p-type channel stop region.
FIG. 20 shows the structure of a Schottky barrier diode 51 with a guard ring. The Schottky barrier diode 51 has a p.sup.+ -type guard ring region 52 along the periphery of a field insulating film 6 isolating a n-type region 4B. An electrode 53 is formed in a Schottky junction on the n-type region 4B, and an electrode 56 is formed in ohmic contact through an n-type contact region 55 with an embedded region 54.
A process for forming the intrinsic base region 19 and emitter region 20 of the npn bipolar junction transistor 24 (FIG. 21D) through the double diffusion of the polycrystalline silicon film 8 in fabricating the high-performance bipolar LSI provided with the npn bipolar junction transistor 24, the lateral pnp bipolar junction transistor 40 (or 42, FIGS. 16 and 18) and the Schottky barrier diode 51 (FIG. 20) with a guard ring includes a step of forming the link base region 14 through the ion implantation of boron at a dose on the order of 10.sup.13 /cm.sup.2, a step of forming the guard ring region 52 of the Schottky barrier diode 51 through the ion implantation of boron at a dose on the order of 10.sup.13 /cm.sup.2 and a step of forming the collector region 32 and emitter region 33 of the lateral pnp transistor through the ion implantation of boron at a dose in the range of 10.sup.13 to 10.sup.14 /cm.sup.2. In most cases, these steps are carried out individually for the following reason.
(i) Since the link base region 14 is formed in a depth as small as possible, so-called parasitic transistor action in the link base region has an influence when the bipolar LSI operates in a high current range. Therefore, portions that acts as a parasitic transistor must be reduced to the least extent by forming the link base region 14 in a small depth and hence the step of forming the link base region 14 is performed as late as possible.
(ii) The guard ring region 52 must be subjected to ion implantation before forming the polycrystalline silicon film 8, which serves as contact electrodes, by CVD.
(iii) The dose of the lateral pnp transistor is higher than those of others to provide a high current amplification factor h.sub.FE by increasing emitter injection efficiency.
The current amplification factor h.sub.FE of the lateral pnp transistor 40 shown in FIG. 16 is reduced due to surface recombination because the current flows mainly along the surface, i.e., the vicinity of the interface of the SiO.sub.2 film 39, and the current amplification factor h.sub.FE is liable to be unstable due to the variation of the surface recombination electrode depending on the condition of the interface of the SiO.sub.2 film 39.
As shown in FIG. 19, the base width W.sub.B of the lateral pnp transistor 42 shown in FIG. 18 is not dependent on the minimum line width achieved by lithography, but is dependent on several factors as expressed by: EQU W.sub.B =a+2b-2c
where a is the minimum line width achieved by lithography, b is the width of overlaps in which the SiO.sub.2 film 19 and the p.sup.+ -type polycrystalline silicon films 43 and 44 overlap each other, and c is the width of areas of side diffusion of the p.sup.+ -type diffused regions of the emitter 32 and the collector 33.
For example, when the minimum line width a=1.2 .mu.m, a stepping projection aligner of .+-.0.3 .mu.m aligning accuracy is employed, and the junction depth X.sub.j of the p.sup.+ -type diffused regions 32 and 33 is 0.2 .mu.m, EQU W.sub.B =1.2 .mu.m+2.times.0.8 .mu.m-2.times.0.8.times.0.2 .mu.m.perspectiveto.2.48 .mu.m
The base width W.sub.B is approximately twice as large as the minimum line width a, and hence it is impossible to provide the lateral pnp transistor 42 with a high f.sub.T.